The present invention relates generally to integrated circuit (IC) designs, and more particularly to a dual port memory device with reduced coupling effect.
FIG. 1 schematically illustrates a typical dual port static random access memory (SRAM) cell 100 that is often used in memory devices for electronic products, such as cellular phones, digital cameras, personal digital assistants, and personal computers. The cell 100 includes two cross-coupled inverters 102 and 104. The inverter 102 is comprised of a pull-up p-type metal-oxide-semiconductor (PMOS) transistor 106 and a pull-down n-type metal-oxide-semiconductor (NMOS) transistor 108. The inverter 104 is comprised of a pull-up PMOS transistor 110 and a pull-down NMOS transistor 112. The sources of the PMOS transistors 106 and 110 are coupled to a power supply through a power line Vcc. The sources of the NMOS transistors 108 and 112 are coupled to a ground or a complementary power supply through a complementary power line Vss. The gates of PMOS transistor 106 and NMOS transistors 108 are connected together at a node 114, which is further connected to the drains of PMOS transistor 110 and NMOS transistor 112. The gates of PMOS transistor 110 and NMOS transistor 112 are connected together at node 116, which is further connected to the drains of PMOS transistor 106 and NMOS transistor 108. The cross-coupled first and second inverters 102 and 104 function as a latch that stores a value and its complement at the nodes 114 and 116, respectively.
A first port pass gate transistor 118 is coupled between a first port bit line BL1 and the node 114. Another first port pass gate transistor 120 is coupled between a first port bit line bar BLB1 and the node 116. A second port pass gate transistor 122 is coupled between a second port bit line BL2 and the node 114. A second port pass gate transistor 124 is coupled between a second port bit line bar BLB2 and the node 116. The gates of pass gate transistors 118 and 120 are controlled by a first port word line WL1. The gates of pass gate transistors 122 and 124 are controlled by a second port word line WL2. The first and second port word lines WL1 and WL2 can be separately selected to turn on the pass gate transistors 118/120 or 122/124 for reading or writing a value from or into the node 114 through the bit lines BL1/BLB1 or BL2/BLB2.
Conventionally, the bit lines, BL1, BLB1, BL2, BLB2, word lines WL1, WL2, power line Vcc, and complementary power line Vss are constructed on the same metal layer in an IC chip. These closely placed conductors induce coupling capacitance, which, in turn, reduces operation speed and increases noise for the memory cell 100. The coupling effect becomes more serious when those conductive lines become closer as the semiconductor processing technology advances.
As such, what is needed is a dual port SRAM device with a reduced coupling-effect.